🚀 go-pugleaf

In article <Apr.27.15.59.55.1989.4457@caip.rutgers.edu> segall@caip.rutgers.edu (Ed Segall) writes:
>
>From your description, this doesn't seem to prove that metastability
>is necessary.  If the state of a line is 0, and it asynchronously
>changes to 1, a carefully designed synchronizer wouldn't mind if the
>transition isn't noticed on the first succeeding clock edge.  Rather,
>it would want either a clean 0 or a clean 1.  If the line stays 1, it
>would definitely want to see a clean 1 by the next edge.  Notice that
But even a carefully designed synchronizer would have a FINITE
probability of failure, even if it is 10e-10.  Those transitions that
occur when the synchronizers samples the line can ALWAYS happen.

>fatal flaw unless you confine the errors to be on transitions only (as
>I explained above).  I think most systems can be designed to handle a
>one-cycle delay in noticing _valid_ transitions.  What they can't
Then again not all systems can handle a one-cycle delay.  And even if
you can use a one cycle delay, the cycle time is reducing over the years
(20MHz -> 33M -> 45M -> ???) and will continue to reduce.  Sooner or
later the cycle time is not going to worth much with a relative slow
synchronizer.
>
>--Ed
>uucp:   {...}!rutgers!caip.rutgers.edu!segall
>arpa:   segall@caip.rutgers.edu

Henry Choy
Advanced Micro Devices, Inc.

Disclaimer: I do not represent the company on the net.