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Article #20971

Re: CDC 205 et al

#20971
From: Mark Nelson
Date: Sun, 30 Apr 1989 21:13
87 lines
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In article <568309@vaxa.uwa.oz> g_ahrendt@vaxa.uwa.oz writes:
>1. In regard to an article posted a while back stating that the CDC CYBER 205 is
>slower than a Cray 1. This is incorrect. The CDC CYBER 205-424 has been clocked 
>around 800 MIPS, making it faster than the Cray 1, ETA10-P, ETA10-Q, NEC SX-1, 
        ^^^^^^^^
>Cray X/MP-2, IBM Sierra 3090-400/VF, NEC SX-1E.....
>
    It's important to make the distinction between MIPS and MEGAFLOPS.
The 205 has a 20-nanosecond clock cycle, making it capable of 50 MIPS
(one instruction issued per clock).  For vector floating point, it
has up to four parallel vector "pipes".  And each pipeline is capable
of performing a simultaneous add and multiply (within strong limitations).
So we're up to 50 * 4 * 2 = 400 MegaFLOPS.  The machine gains another
factor of 2 by going to 32-bit floating point data instead of the normal
(for supercomputers) 64-bit floating point.  That gives a peak of
800 MegaFLOPS, but 50 MIPS.
    Looking at another uniprocessor, the NEC SX-2 has a 6-nanosecond
clock (167 MIPS), 4 pipes, and two operations per pipe yielding
167 * 4 * 2 = 1,333 MegaFLOPS.
    For comparison purposes, the Cray-1 gives: 12.5-nsec clock = 80 MIPS
with 2 operations/clock yielding 160 MegaFLOPS.

Going on to multi-processor machines:

Machine      Clock   MIPS  Pipes  FLOPS/  Processors   32-bit      Total
             (nsec)               pipe                 speed-up  (MegaFLOPS)
Cray X-MP/4   8.5    118            2           4                    941 
Cray-2        4.1    122*           2           4                   1951
ETA-10G       6.5?   154     2      2           8         2         9846
Cray Y-MP/8   6.     167            2           8                   2667
NEC SX-X      2.9    345     4      4??         4                  22069

Notes:
MIPS  I'm referring to MIPS in one processor.
*  The Cray-2 issues instructions at most every other clock period
   so this is the actual peak MIPS/processor.  For vector instructions,
   results are produced every clock cycle.
?  I'm not positive about this number.  Can anybody tell me what the
   fastest clock cycle on any shipped ETA machine is?
?? Since the SX-X is still the apple in a corp (pun intended) of NEC
   engineers' eyes, I don't have very complete information about it.
   I have numbers for all the other columns for the SX-X, but without
   this fudge factor I can't get them to work out.

   I'm sorry if I left out your favorite machine--these were the only
machines I knew the numbers for off the top of my head, other than the
Cray-3, and since I work for Cray I didn't feel it would be appropriate
to comment on unreleased Cray machines (numbers for the Cray-3 are
easily available).
    Remember that theses are peak speeds for the machines; sort of
computational speeds of light, and average performance for any mix
of programs is likely to be much lower.

>2. A second article displayed the following :
>> ...
>
>This is also incorrect, whereas the following gives a more accurate picture, 
>based on machines actually available, and not scheduled for production.
>
>1. ETA               US 10-G       10.3 Billion Instructions per Second 
   I get 1230 MIPS
>2. Thinking Machines US CM-2       10   Billion Instructions per Second
>3. West German Govt. D  Suprenum 1  5   Billion Instructions per Second
>4. ETA               US 10-E        3.4 Billion Instructions per Second
          760 MIPS (10.5 nsec clock 8 processors)
>5. NEC               J  SX-X44      3.2 Billion Instructions per Second
         1380 MIPS (not yet available) 
>6. Cray              US X/MP-416    2.8 Billion Instructions per Second
          470 MIPS (basically no longer available new)
>7. Thinking Machines US CM-1        2   Billion Instructions per Second
>8. NEC               J  SX-2        1.3 Billion Instructions per Second
          167 MIPS
9. Cray               US Y-MP
         1333 MIPS

     I've never seen any numbers on the Suprenum project, so I can't
comment on it.  I don't have any of the details on the Thinking Machines
CM-1 and CM-2 with me (I'm home, they're at work) so all I can say is
that since they are SIMD architectures the above BIPS numbers can't
be right, although the numbers might be right for BOPS.  By the way,
Thinking Machines has great sales brouchures--at least one even has
moving parts.


Mark Nelson                 ...!rutgers!udel!nelson or nelson@udel.edu
This function is occasionally useful as an argument to other functions
that require functions as arguments. -- Guy Steele
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From: nelson@udel.EDU (Mark Nelson)
Newsgroups: comp.arch
Subject: Re: CDC 205 et al
Keywords: MegaFLOPS
Message-ID: <14353@louie.udel.EDU>
Date: 30 Apr 89 21:13:44 GMT
References: <568309@vaxa.uwa.oz>
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Organization: University of Delaware and Cray Research
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