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Article #2098

Re: Parity hardware for uninitialized variable checking?

#2098
From: David Callahan
Date: Sun, 03 Sep 1989 15:52
33 lines
2451 bytes
In article <11347@burdvax.PRC.Unisys.COM> barry@PRC.Unisys.COM (Barry Traylor) writes:
>On Unisys A Series systems (formerly Burroughs B5/6/7000 series), all words
>have tags.  These tags are not part of the data portion of the word;
>different tags have different uses.  One of the tag enumerations is 6.  
>With this tag, all non-privleged load operations fault and all non-privileged 
>store operations complete OK.  Some, but certainly not all of the A Series 
>languages take advantage of this feature.

The Horizon architecture researched at the Supercomputing Research
Center and now in commercial development at Tera Computer Co has 
4 data trap bits associated with each word of memory. Generally access to
a word with one of these bits set will cause the accessing stream 
to take a trap (which in this architecture is basically an unexpected
branch to a user-specified location). Eight bits in the 64-bit pointer
modify this behavior: for each trap bit there is a pair of bits that
suppress the trap on read and write respectively.

These bits could be used to detected uninitialized access: a read
that traps is an error while a write that traps simply clears the bit
and is restarted. This wasn't really the intent of these bits, they
were designed more for type-tagging and demand-driven evaluation.

In the context of this thread of discussion (debugging C-ish
langauges) two uses are immediate: very efficient data break points
set by a debugger and protection of implementation data structures
(such as tables & lists maintained by malloc()).

David Callahan  (david@tera.com, david@june.cs.washington.edu,david@rice.edu)
Tera Computer Co. 	400 North 34th Street  		Seattle WA, 98103

-- 
David Callahan  (david@tera.com, david@june.cs.washington.edu,david@rice.edu)
Tera Computer Co. 	400 North 34th Street  		Seattle WA, 98103
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Message-ID: <9117@june.cs.washington.edu>
Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!uw-june!david
References: <12.filbo@gorn.santa-cruz.ca.us> <4322@druhi.ATT.COM> <14166@polyslo.CalPoly.EDU> <11347@burdvax.PRC.Unisys.COM>

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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!uw-june!david
From: david@cs.washington.edu (David Callahan)
Newsgroups: comp.arch
Subject: Re: Parity hardware for uninitialized variable checking?
Keywords: tags, A Series
Message-ID: <9117@june.cs.washington.edu>
Date: 3 Sep 89 15:52:27 GMT
References: <12.filbo@gorn.santa-cruz.ca.us> <4322@druhi.ATT.COM> <14166@polyslo.CalPoly.EDU> <11347@burdvax.PRC.Unisys.COM>
Reply-To: david@tera.com (David Callahan)
Distribution: usa
Organization: Tera Computer Co., Seattle WA
Lines: 33