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Article #21037

Re: Criteria for comparing RISC processors

#21037
From: Mike Pogue
Date: Wed, 03 May 1989 13:16
34 lines
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In article <102441@sun.Eng.Sun.COM> jek3@sun.UUCP (Joseph Kowalski) writes:
>R2000 at 8 Mhz (or other sadism), but I feel that the following is a much
>more meaningful comparison than 'Mhz for Mhz':
>
>	Compare performance on the highest performing currently available
>	implementation of an architecture in a given technology
>
>I realize that 'Mhz for Mhz' has more meaning in the RISC, ONE INSTRUCTION PER
>CLOCK world than in the CISC world, but even this is doubtful.
>
   Over time, MIPS, SPARC, and the 88K will all have pretty much the same 
clock rates, and will use the same feature sizes.

   When we decided to go RISC, we evaluated all three of these technologies,
and finally decided that they were pretty similar architecturally.  The 88K
had better multiprocessor hooks, but that was a relatively minor consideration.

   THe bottom line was:  who has the best chance of succeeding in the long run?
A small company like MIPS, a company that can't decide whether it wants to sell
chips or not (SPARC), or a big company that has succeeded once before (with
the 68K series) that knows the business (MOTOROLA)?  For us, it was pretty simple.

   If you compare performance on a weekly basis, you will find yourself flipping
between vendors.  What our customers have been asking for is a solid RISC, spanning
a wide range of systems, supported by a solid chip vendor, and a company that
knows how to build a wide range of systems (not just point products).

   Architecturally, you HAVE to compare Mhz for Mhz, or you are not looking at
architecture.

   Mike Pogue
   Data General Corp.
   
   These opinions are my own....
Technical Details
Message-ID: <156@dg.dg.com>
Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!dg!mpogue
References: <2368@ogccse.ogc.edu> <1464@cfa.cfa.harvard.EDU> <141@dg.dg.com> <18120@winchester.mips.COM> <144@dg.dg.com> <18316@winchester.mips.COM> <147@dg.dg.com> <18653@winchester.mips.COM> <102441@sun.Eng.Sun.COM>

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!dg!mpogue
From: mpogue@dg.dg.com (Mike Pogue)
Newsgroups: comp.arch
Subject: Re: Criteria for comparing RISC processors
Message-ID: <156@dg.dg.com>
Date: 3 May 89 13:16:23 GMT
References: <2368@ogccse.ogc.edu> <1464@cfa.cfa.harvard.EDU> <141@dg.dg.com> <18120@winchester.mips.COM> <144@dg.dg.com> <18316@winchester.mips.COM> <147@dg.dg.com> <18653@winchester.mips.COM> <102441@sun.Eng.Sun.COM>
Reply-To: mpogue@dg.UUCP (Mike Pogue)
Organization: Data General, Westboro, MA.
Lines: 34