🚀 go-pugleaf

In article <17932@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes:
>>>A couple of years ago there was an article in Byte about a proposed design
>>>which they called WISC for Writeable Instruction Set Computer.
>
>>Honeywell and Buro..whoops UNISYS had mainframes like this, well over
>>a decade ago. Byte, lives at the cutting edge....
>
>The original complaint that "RISC machines use too much memory bandwidth"
>is where the problem with the whole argument lies.  The correct assertion
>is that "high-performance machines use too much memory bandwidth."  That

>Soft machine or "WISC" is a bad idea because a truly horizontal
>microarchitecture is not amenable (enough) to automatic instruction-set
>customization.  Going to a vertical microarchitecture to make the job

This is probably true in the general case, but not true for
special-purpose.  For example, suppose vectors represent a high
percentage of the application.  Wide-word microcode can prefetch a
vector element, increment the address pointer, issue a FP MUL, issue a
FP ADD, decr the loop count, and conditionally branch in one cycle, in
microcoded vector machines and (I hope) in the generic RISC/VLIW.
Clearly, this function will execute many times faster than on a RISC
which takes one to two cycles to do each step mentioned above.

"WISC" machines would be intended for this kind of application, where
the attempt would be to build a general purpose box which is
customizable to be cost-effective competing with special-purpose
boxes.  Clearly, this requires the application to be characterized by
spending most of its time in a small set of functions which can be
sped up a lot by micro-parallelism, as in the case of a vector
instruction set.

I know that there is probably no CISC instruction set that makes grep,
troff or dhrystone run significantly faster than the fast RISC-based
boxes.  But that is not where my computing bottlenecks are; mine
involve SPICE, logic simulation, fault grading, and stuff like that.
-Stan