Article View: comp.arch
Article #21103Re: WISC (Bandwidth and RISC vs. CISC)
From: Stanley Chow
Date: Mon, 08 May 1989 00:22
Date: Mon, 08 May 1989 00:22
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1196 bytes
In article <17933@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes: >>Well, what do people think [about WISC]? > >>I know it's a lot of trouble, but you could relieve a lot of the pressure >>that RISC puts on the icache (and consequently the memory bus). > >The point I want to make is that if RISC (or anything else) keeps the >instruction cache 100% busy, THAT IS GOOD, NOT BAD. Actually, it is bad. Keeping the i-cache 100% busy means it is the bottle neck, so the original argument applies. Stanley Chow BitNet: schow@BNR.CA BNR UUCP: ..!psuvax1!BNR.CA.bitnet!schow (613) 763-2831 ..!utgpu!bnr-vpa!bnr-fos!schow%bnr-public I am just a small cog in a big machine. I don't represent nobody.
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!bnr-vpa!bnr-fos!bnr-public!schow From: schow@bnr-public.uucp (Stanley Chow) Newsgroups: comp.arch Subject: Re: WISC (Bandwidth and RISC vs. CISC) Message-ID: <480@bnr-fos.UUCP> Date: 8 May 89 00:22:42 GMT References: <10978@polyslo.CalPoly.EDU> <17933@cup.portal.com> Sender: news@bnr-fos.UUCP Reply-To: schow%BNR.CA.bitnet@relay.cs.net (Stanley Chow) Organization: Bell-Northern Research, Ottawa, Canada Lines: 17