Article View: comp.arch
Article #21166Re: ESD protection (was Re: Do you have bandwidth?)
From: David Boreham
Date: Tue, 09 May 1989 16:07
Date: Tue, 09 May 1989 16:07
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Several posters have refered to removing ESD protection on chip pads, and alluded to consequent speed advantages. Mabe I'm missing something but as far as I know the reason why off-chip signals are slower than on-chip ones is a combination of the following: 1) Much larger capacitance (25pf minimum or 50--100 pf for busses). 2) The need to drive current. 3) The need to drive over a wide voltage range (0--5v) in order to be compatible with TTL devices. 4) Off-chip signals need to be tested on a tester. Testers are not generally capable of resolving very accurate timing (on microprocessors) and require large (50pf or so) capacitances to be driven during testing. I think these are probably ranked in order of importance. ESD must surely be less important than these. -- David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos-c!davidb +44 454 616616 ex 543 | Internet : @col.hp.com:davidb@inmos-c
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wasatch!cs.utexas.edu!uunet!mcvax!ukc!warwick!inmos!davidb From: davidb@inmos.co.uk (David Boreham) Newsgroups: comp.arch Subject: Re: ESD protection (was Re: Do you have bandwidth?) Keywords: protection static ESD Message-ID: <1450@brwa.inmos.co.uk> Date: 9 May 89 16:07:39 GMT References: <407@bnr-fos.UUCP> <7766@thorin.cs.unc.edu> <418@bnr-fos.UUCP> <6658@cbmvax.UUCP> <396@dalcsug.UUCP> <18682@gumby.mips.COM> Reply-To: davidb@inmos.co.uk (David Boreham) Organization: INMOS Limited, Bristol, UK. Lines: 23