Article View: comp.arch
Article #21169Re: Semaphores
From: aglew
Date: Wed, 10 May 1989 15:18
Date: Wed, 10 May 1989 15:18
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>aglew@mcdurb.Urbana.Gould.COM writes: > >> Apparently the ARM does something similar, only checking for interrupts >> at branches. > >This is not correct. ARM checks for interrupts at the end of each and every >instruction. The store multiple register instruction allows a warped sort of >semaphore instruction to be built, and the new ARM3 (VL86C020) has an >uninterruptable memory to register SWAP instruction for just this purpose. > > >Steve Furber sfurber@acorn.uucp > Acorn Computers Ltd, England. Sorry, I confused the Transputer with the Acorn.
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arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!unmvax!deimos.cis.ksu.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglewReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!unmvax!deimos.cis.ksu.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglew From: aglew@mcdurb.Urbana.Gould.COM Newsgroups: comp.arch Subject: Re: Semaphores Message-ID: <28200309@mcdurb> Date: 10 May 89 15:18:00 GMT References: <759@acorn.co.uk> Lines: 17 Nf-ID: #R:acorn.co.uk:759:mcdurb:28200309:000:564 Nf-From: mcdurb.Urbana.Gould.COM!aglew May 10 10:18:00 1989