🚀 go-pugleaf

In article <241@ssp1.idca.tds.philips.nl>, roelof@idca.tds.PHILIPS.nl (R. Vuurboom) writes:
> But maybe we can second-guess motorola. How about the following scenario:
> 
> In order to improve perfomance, motorola decides to pipeline heavily,
> heavy pipeline means a lot of data prefetching. Now with all that
> prefetched data we suddenly run into an exception...problems. Best thing
> is throw it all away and start anew. Now the whole point of instruction
> continuation was to know which locations were already accessed. Since this 
> could no longer be supported might as well go over to  the simpler 
> instruction restart. So the real trade-off was performance vs virtual 
> machine support.

The 68000 was designed with three stages of prefetch, all controlled by
microcode.  The microcode was free to manage the prefetch, external bus,
and internal data operations in any order.  The actual order was determined
by the microcode, optimizing for performance.  The values of user visible
registers could be invalid, while current values were held in temporary
registers.

Although virtual memory was desired for the 68000, it was deemed too costly
to provide an instruct restart model.  This required many more temporary
registers and data paths to capture user visible values at the instruction
dispatch, and to restore them at a bus error.  The option of restricting
the microcode usage of temporaries and control of the prefetch would have
impaired the performance of the processor.

After the 68000 went to market, the instruction continuation model was
conceived.  This is best understood as an interrupt at the microcode level.
The "stack dump" is a context switch, and the RTE which does the stack
restore is a context switch back.  This model required only a few new
registers, and only one new data path.  This same data path formed the
basis for the 68010 loop mode.

Presumably, in later processors from the family, the provision of extra
hardware to reduce instruction cycle counts also leads to a reduction
in the indeterminancy of the values of registers.  This makes the cost
of instruction restart more tractable.

-John Zolnowsky				...!sun!johnz or johnz@sun.com