🚀 go-pugleaf

In article <25294@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:

>The chart supplied shows R2000 based systems falling in
>at about MIPS = 2/3 MHz, with R3000 based systems at MIPS = 8/10 MHz.
>(1 data point, but you could also look at claims by other companies using
>the Mips CPU's...)  

>What is the explanation for this change?

Real easy: the original R2000 had the simplest possible cache control
(since, at that point, doing the cache control on-chip for off-chip
caches was untriewd), i.e., cache-line = 1 32-bit word, refill 1 word
on cache miss; store-thru cache with invalidation of word upon
partial-word writes.

The R3000 added:
	multi-word refill, 4-32 words upon cache-miss
	instruction-streaming, where you try to execute instructions as
		they're refilled on a miss, as much as you can
	choice of partial-word invalidate or read-modify-write; for systems
		with long-memory latency, the latter is a good thing,
		as the refill penalty is much worse.
The MHZ/VUPs went from 1.5-1.6 (in M/500, M/800, M/1000), to 1.3-1.4
on the M/120 (still R2000, but faster memory system), to 1.2-1.3 (R3000,
but in big-memory, high-concurrency, inherently longer latency design).
If you put an R3000 in a short-bus, low-latency design [i.e., workstation
or smaller server, not big server], you'd expect the MHZ/VUPs to drop
some more.
As usual, you really have to work hard to scale up performance
with the clock rate...

Anyway, those are the reasons; nothing mysterious.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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