🚀 go-pugleaf

In article <25602@amdcad.AMD.COM> rpw3@amdcad.UUCP (Rob Warnock) writes:
>[..] Since with the Am29000, "spilling"
>a few regs to memory to make room for a new subroutine context usually
>does not cause a matching "fill" when the routine returns [those 128 local
>regs give you a *lot* of hysteresis], the interesting "knee of the curve"
>is in the tradeoff between cache spill/fill traffic and register cache size.
>That is, how much incremental spill/fill traffic do you save (thus incremental
>bus bandwidth saved and thus performance gained) for each additional register
>you put in the stack cache?

relatedly i had to admire sun installing compiler tricks to turn tail-
recursive C into iterative C.