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Article #21251microprocessor 2nd-level cache protocols for multiprocessing
From: Mark Smotherman
Date: Mon, 15 May 1989 02:33
Date: Mon, 15 May 1989 02:33
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976 bytes
Is there any developing consensus concerning second-level cache consistency protocols in multiprocessor environments for 486 and 68040? E.g. are the manufacturers such as Intel, Motorola, etc. going to use something like MOESI in 2nd-level cache chips? Or, do such protocols vary markedly from system to system even given the same processor and availability of cache controller chips from the processor manufacturer? -- Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634 INTERNET: mark@hubcap.clemson.edu UUCP: gatech!hubcap!mark
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!cwjcc!gatech!hubcap!mark From: mark@hubcap.clemson.edu (Mark Smotherman) Newsgroups: comp.arch Subject: microprocessor 2nd-level cache protocols for multiprocessing Keywords: cache consistency coherency Message-ID: <5481@hubcap.clemson.edu> Date: 15 May 89 02:33:11 GMT Organization: Clemson University, Clemson, SC Lines: 9