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Article #21263

A little bit of data on register usage...

#21263
From: Mike Newton
Date: Sun, 14 May 1989 06:44
38 lines
2172 bytes
There has been a long conversation "Re: 80486 vs. 68040 code size"
in this group lately, with various charges, assumptions and opionions
abour register usage.  I'd like to add a little (!) bit of data to
this argument.  My experience comes from writing optimizers and
highly optimizing compilers for several different projects.

One project was a Prolog compiler.  It produced code that ran
"naive reverse" (not a good benchmark, but not as bad as "deterministic 
append") at approximately 1MegaLip on an IBM 3090.  Another group in
France completed a similar project.  In each case the limit of 16 general
purpose (non-fp, non-machine-control) registers was an impediment.
My calculations yielded a 20-25% improvement if we had had 4 more
registers.

Work on 'portable' (not really, but...) C optimizers made it very
clear that for both the 80386 and 68020,  more registers would
be very useful for nested loops and other complicated procedures.  This
is the kind of code that often does not show up in benchmarks, but
that can make 'real' (now i'm really getting vague...) programs run
fairly slow.

Give me 32 GP registers any day.... but dont define "GP" the way Intel does.

- mike

Please pardon a double signature it it exists... this is the first
posting from our new news system, so it's also serving as a test.

-- 
	From the bit bucket in the middle of the Pacific...

Mike Newton				newton@csvax.caltech.edu
Caltech Submillimeter Observatory	kahuna!newton@csvax.caltech.edu
Post Office Box 4339
Hilo Hawaii 96720			808 935 1909

	"Reality is a lie that hasn't been found out yet..."
	
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From: newton@kahuna.submm.caltech.EDU (Mike Newton)
Newsgroups: comp.arch
Subject: A little bit of data on register usage...
Message-ID: <3930@uhccux.uhcc.hawaii.edu>
Date: 14 May 89 06:44:51 GMT
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