🚀 go-pugleaf

In article <19661@winchester.mips.COM> mash@mips.COM (John Mashey) writes:

>(or anybody else really familiar with supercomputer architecture)
>could describe the memory systems of such things.  There are some
>fairly sensible reasons why the answers on 3A & 3B might be
>opposite....

That reminds me.  We have seen some postings recently to the effect that
connection technology is going to allow chips with some really large numbers
of inputs/outputs.  When is someone going to stop spending so much time on
the "easy" :-)   part of building what used to be a supercomputer in VLSI (CPU
speed), and start spending some time on the hard part - fast multiport
interleaved memory.  I would like to see someone come up with a cheap fast
multiport memory interconnect.  

For example, a Cray Y-MP has 4 ports/CPU, with 8 CPU's,
for a total of 32 CPU ports, 256 banks of memory in 32 MWords, with a 5
Clock period cycle time per bank (6 ns/clock).  The memory interconnect can
accept one memory operation per 6 ns clock (read or write) on each port, for
a total memory bandwidth (excluding bank conflicts) of 340 Gbits/second.
There are 32 1MW memory modules.  Access time is 15 ns, SECDED is implemented
on 64 bit words.

A reasonably inexpensive micro based system might need 4 CPU ports, 4
memory banks, and operating at 10ns (To handle all those 100 MHz RISC
processors that everyone says are coming.)  If we don't do something, we
are going to keep building what someone I know refers to as "The World's
Fastest Toy Computer".

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117