🚀 go-pugleaf

In article <28200315@mcdurb> aglew@mcdurb.Urbana.Gould.COM writes:

| Now you're talking!!!  Lots of pins give us multiple ports - now how do we
| use them?

  Let's look back a few years... the GE600 mainframes had eight port
memory controllers. You could connect any combination of CPU's and I/O
controllers (doing DMA) as long as you had at least one of each. The
cache was on the memory controller.

  If we update that to today's micro world, we could call it an
inteligent cache and bus controller or something. No problems of cache
validity between CPU's, the controller does it. Interleave? The
controller could interleave from multiple sources, write diferent
channels to diferent banks, etc.

  The problem I see is the bus. The mainframes had fat cables, and
could have an address and data path for each memory port. The i/o
controller(s), something like a DMA controller, had individual cables
going to the disk controller, tape controller, etc. Each device
controller had cables going to each device, which is still done today.

  What resulted was a "data tree," with multiple devices on each
controller, multiple device controllers going to the i/o controller,
multiple i/o controllers and CPU's going to the memory controller.
Everything having to do with the memory subsystem, the data, cache,
interleave, etc, was all controlled by the memory controller,
eliminating problems of cache validity between subsystems.

  To make use of this would require some new packaging, either going to
cables or a very complex bvus with multiple data and address
connections. This is more traditional on minis.

  I'm sure there are other ways to use multiport memory, but this is
certainly one which has proven useful.
	bill davidsen		(davidsen@crdos1.crd.GE.COM)
  {uunet | philabs}!crdgw1!crdos1!davidsen
"Stupidity, like virtue, is its own reward" -me