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Article #21340

Re: microprocessor 2nd-level cache protocols for multiprocessin

#21340
From: Dave Kirk
Date: Thu, 18 May 1989 14:35
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In article <GRUNWALD.89May17121636@flute.cs.uiuc.edu> grunwald@flute.cs.uiuc.edu (Dirk Grunwald) writes:
>
>What's the MOESI protocol for cache consistency?
>--
>Dirk Grunwald
>Univ. of Illinois
>grunwald@flute.cs.uiuc.edu

The MOESI protocol is the proposed cache consistency scheme to be used
with FUTUREBUS.  It derives its name from the five states a cache/memory
line can assume.  If my memory serves me correctly, they were:
	M: Master
	O: Owner
	E: Exclusive (exclusive owner)
	S: Shared
	I: Invalid
The protocol seems to be closely related to Jim Goodman's Write Once
Policy.  In fact, I think Jim was involved with the MOESI group.  The
protocol allows almost any type of device to occupy a position on the
Futurebus (i.e. a device with no cache, a device with write-through cache,
a device with copy-back cache ...).  More information on this can
be found in IEEE Futurebus 896.2 document, or there was a paper by
Sweazy (i'm going on memory here!) that was published.  If anyone
needs a full reference just send me email.

Dave Kirk  kirk@maxwell.ece.cmu.edu
-- 
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From: dkirk@k.gp.cs.cmu.edu (Dave Kirk)
Newsgroups: comp.arch
Subject: Re: microprocessor 2nd-level cache protocols for multiprocessin
Message-ID: <5021@pt.cs.cmu.edu>
Date: 18 May 89 14:35:12 GMT
References: <5481@hubcap.clemson.edu> <18451@cup.portal.com> <GRUNWALD.89May17121636@flute.cs.uiuc.edu>
Distribution: comp
Organization: Carnegie-Mellon University, CS/RI
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