🚀 go-pugleaf

In article <26207@ames.arc.nasa.gov>, lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:
> I agree.  I would like to make a request here- I think the time has come
> for micro people to consider mainframe architectural requirements.  Some
> nice micros have come out in recent years which could have been extended
> to mainframe architectures except for various flaws which, if remedied, would
> have had little or no effect on the performance or usability as micros.
> 
> Next time, while designing a new architecture, ask if anything will stop you
> from building a high performance implementation with:
> 
> a clearly and completely defined instruction set architecture 
> support for a large number of processors in a symmetric arrangement
> separate caches for each processor
> a high bandwidth multi-port multi-bank central memory
> high bandwidth I/O

And support for high availability - error detection and recovery. yes, much 
of that is implementation but it must be supported by the proper architectural
definition.  

And support for high multiprogramming levels - without getting into the wars
about how long it takes to save registers (not very) - the effect on caches,
TLBs, etc. is far more relevant.

And support for continuous operation - dynamic change to system configuration.

And support for multilevel memory hierarchies - possibly processors cache,
global cache, main storage, bulk RAM.

And support for performance measurement and system management.

We could start a whole new debate - what is a mainframe?  We make them
but I'm not sure that there is a well-understood definition.

-- 
Mike Taylor                               ...!{hplabs,amdcad,sun}!amdahl!mat

[ This may not reflect my opinion, let alone anyone else's.  ]