🚀 go-pugleaf

In article <6951@cbmvax.UUCP> jesup@cbmvax.UUCP (Randell Jesup) writes:
>In article <1450@brwa.inmos.co.uk> davidb@inmos.co.uk (David Boreham) writes:
>>Several posters have refered to removing ESD protection on chip
>>pads, and alluded to consequent speed advantages. Mabe I'm missing
>>something but as far as I know the reason why off-chip signals are
>>slower than on-chip ones is a combination of the following:
>>
>>1) Much larger capacitance (25pf minimum or 50--100 pf for busses).
>
>	Actually, I believe ESD is the prime reason for (1) above, so it
>is the biggest target (for very high speed designs).
>
>	Of course, I'm just a software guy, what do I know?  ;-)
>
>-- 
>Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup

Both of you are right (and wrong :-)). The ESD protection diodes are a
significant source of the capacitive load which the inputs present to a
transmission line; but, since we do have to think of transmission lines
(and it seems like few designers/engineers using MOS or TTL circuits *do*
think that way) we must also consider the capacitive load which the outputs
must drive. On a poorly-designed circuit board (or whatever) this can
represent significantly more capacitance than the fan-out count of all
of the inputs would indicate.  This necessitates some rather large buffers
on the outputs, which means greater power dissipation; and MOS, in
particular, tends to slow down as it heats up. There's still no free lunch.

Interestingly, to me at least, we find that the biggest problem with the
*really* high speed circuits (500MHz to 1.2GHz ECL) is that the lead
inductance of the high-pin-count packages is the real killer. At first
blush, TAB seems the way to go.

Regards,

-- 
Ron Widell, Field Applications Eng.	|UUCP: {...}mcdchg!motmpl!ron
Motorola Semiconductor Products, Inc.,	|Voice:(612)941-6800
9600 W. 76th St., Suite G		| I'm from Silicon Tundra,
Eden Prairie, Mn. 55344 -3718		| what could I know?