Article View: comp.arch
Article #2145Re: Parity in Internal Data Paths of Processors
From: bob larson
Date: Fri, 08 Sep 1989 09:15
Date: Fri, 08 Sep 1989 09:15
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1326 bytes
In article <124311@sun.Eng.Sun.COM> kum@sccmts.Sun.COM (Kumar Venkatasubramaniam) writes:
>Apart from the obvious use in
>detecting errors in memory data and errors in long buses
>susceptible to noise, does anyone know of parity being
>carried through the internal paths of a processor?
Prime does use parity on internal busses. Cache parity errors on
prime machines with write-through cache cause the data to be re-read
from main memory. (Main memory is ECC, of course.) Uncorrectable main
memory errors will do a page fault if the page is on disk.
(This refers to recent members of the 50 series, not ancient history
or machines from other companies sold under the Prime label.)
--
Bob Larson Arpa: blarson@basil.usc.edu
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Prime mailing list: info-prime-request%ais1@usc.edu
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!usc!basil.usc.edu!blarson From: blarson@basil.usc.edu (bob larson) Newsgroups: comp.arch Subject: Re: Parity in Internal Data Paths of Processors Keywords: parity, error detection Message-ID: <19776@usc.edu> Date: 8 Sep 89 09:15:45 GMT References: <124311@sun.Eng.Sun.COM> Sender: news@usc.edu Reply-To: blarson@basil.usc.edu (bob larson) Organization: USC AIS, Los Angeles Lines: 19