🚀 go-pugleaf

>> In the midst of a lively debate, folks started talking about:
>> >>Consider that the 25Mhz R3000 requires two bus transactions per clock 
>> >>cycle, effectively running the bus at 50Mhz.
>> in the interest of educating ME, what's a "bus transaction"?
>> in other words, is a bus "transaction" any more exalted a thing than a
>> bus "cycle"?

The poster you are responding was playing a word game.  "Transaction"
is a general term, and can apply to something as simple as a single
transfer, but carries the exaltedness implication.  It was to make the
MIPS uP sound stupid, that it has a double-cycled bus, which, in
turn, could be a barrier to future cycle time reductions.

Of course, the poster was mixing "architecture" with "implementation,"
a common mistake.  And marketing ploy.  I will give odds that future
MIPS implementations will not have time multiplexed busses if it
doesn't make sense, but still be architecturally compatible at the
instruction set level.

-Stan				Disclaimer: Do I have an opinion yet?