🚀 go-pugleaf

In article <19755@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>There have been a number of discussions on such issues of late.
>Here are a few useful papers, both from ASPLOS III (ACM SIGPLAN Notices,
>May 1989): [mention of Wall & Jouppi, and Smith, Johnson & Horowitz]

Don't forget Glenn Hinton's Spring Compcon paper, which discusses the
microarchitecture and implementation strategy for Intel's next generation
960.  It is capable of dispatching instructions at a sustained rate of
2 instructions per clock (i.e. 0.5 cycles/instruction), and thus capable
of executing certain algorithms (matrix mul, bresenham, fft) from on-chip
instruction cache at a rate of 66 native MIPS.  The architecture can
dispatch up to three instructions in any cycle: one normal register-register
instruction, one memory instruction (load or store), and one branch.
The implementation includes static branch prediction, 8+ frames (of 16)
of cached registers, and a number of other features.

It is no accident that both papers mentioned by John Mashey conclude that
2-3 instructions/cycle is the practical limit for this generation of
superscalar processors.  Expect to see Intel announce the first true
superscalar microprocessor implementation sometime this year.

If you want to hear more about it, come to my talk at the "Hot Chips"
IEEE symposium at Stanford later in June.  I will be discussing the
architectural support in the 960 for superscalar implementations, as
well as the microarchitecture that implements these features.

S. McGeady
Intel Corp.