Article View: comp.arch
Article #21520Re: Programming (was Register usage
From: aglew
Date: Fri, 02 Jun 1989 02:14
Date: Fri, 02 Jun 1989 02:14
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870 bytes
>The cut line for scratch registers is directly proportional to the memory >latency. The longer your latency the more registers, and concurrently >handled computation, you need to mask it. > > >brooks@maddog.llnl.gov, brooks@maddog.uucp I should probably learn to shut up before I have published my research, but... scratch registers do not necessarily have to appear as register numbers in the instruction set.
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arc1-ca.pugleaf.net!utzoo!utgpu!utstat!jarvis.csri.toronto.edu!rutgers!deimos.cis.ksu.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglewReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!utstat!jarvis.csri.toronto.edu!rutgers!deimos.cis.ksu.edu!uxc!uxc.cso.uiuc.edu!mcdurb!aglew From: aglew@mcdurb.Urbana.Gould.COM Newsgroups: comp.arch Subject: Re: Programming (was Register usage Message-ID: <28200327@mcdurb> Date: 2 Jun 89 02:14:00 GMT References: <10534@ihlpb.ATT.COM> Lines: 11 Nf-ID: #R:ihlpb.ATT.COM:10534:mcdurb:28200327:000:414 Nf-From: mcdurb.Urbana.Gould.COM!aglew Jun 1 21:14:00 1989