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>In article <479@unicads.UUCP> les@unicads.UUCP (Les Milash) writes:
>
>Somebody recently also pointed out that the INMOS Transputer can c-switch
>in .6uS.  The way they do it is sort of like this but wierder;
>and it's different-but-related wrt this thread:
>there are 6 registers, a PC, a FP, and a 3-or-4 deep hardware stack.
>all local variables are in "memory", and they have fast FP+short
>offset addressing mode.
>
>remember the TI 99*?  before my time, but it's a memory-to-memory machine,
>with the "registers" being memory-mapped, FP relative.

The ATT CRISP chip is similar; its actually a memory-memory architecture, 
where all references are relative to a stack pointer. The top 32 entries are
cached in a Tos-of-Stack cache. This is like a register-window, with a
granularity of one register (i.e. window slides by 1 min, instead of fixed 8),
and with the advantage that you can address into the registers.

A context switch can be extremely fast; just change the stack pointer. Of 
course, then all accesses to the 'registers' are cache misses.

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