🚀 go-pugleaf

>[Brooks]
>Needless to say, when the application starts missing cache (for any of the
>microprocessors) the performance rapidly drops into a hole when compared to the
>classic supercomputer.  The microprocessor vendors now need to learn the last
>lesson in supercomputer architecture, which is getting adequate main memory
>bandwidth.  Since interleaving memory chips with glue logic would raise cost
>too much, the micro vendors need to get in close collaboration with the memory
>chip vendors to get the interleaving done on the memory chips themselves.  This
>may be a good way for the U.S. manufactures to get back into the memory chip
>biz.  Design your micro with interleave control on the chip and then design
>your memory chips that have a compatible arangement, then don't tell the
>foreign memory chip vendors about the micro/memory chip interface until you
>get to market.  Interleaving on the memory chip is not a difficult thing to do,
>one only has to decide that it is time to do it.

So, we're back to memory again. I hesitate to get involved, since we all 
heard Mark Johnson saying "Don't talk about, buy it!", to us intellectual
weenies who can only talk about things - but I can only talk about it for
the moment, so here goes:

Q:  how many processor chip vendors will be willing to tie themselves
    tightly into a memory manufacturer?  Well, there are some companies
    who do both...  but are you going to risk customers refusing to
    buy your processor chip because they have to use your memory chips
    with it?
Prediction: people will be very slow to get into tightly coupled 
    processor/memory.  But when they do, the processor companies will 
    probably put out both custom memory and non-custom memory processor
    chips - probably by last stage customization of the die. Ditto memory.
    This will probably be suboptimal.