🚀 go-pugleaf

Data General claims that the ECL implementation of the Motorola 88000 
family of processors is 100% compatible with the CMOS version 
ie. 88100, 88200 (ref. Compcom Spring '89).
The partitioning of the two implementations is different and lead
to interesting decisions. For example in the ECL version, the FPU
is implemented on a separate chip (vs same chip in the CMOS version). 
Being on a separate chip, the latency of accessing the register
file located on the integer unit became too long so DG apparently 
decided to put a "copy" of the 5-port register file on the FPU as well.
In the CMOS implementation there is a single register file shared
by the integer unit and the Special Function Unit 1 (FPU).

This leads to the following question:
How is consistency maintained between the two register files?
In the ECL implementation are writes copied between the two register files? 
If so, it must generate a lot of traffic between the two chips.
Notice that the consistency has to be maintained in hardware since
the two implementations are object code compatible.

					Marc Tremblay
					marc@CS.UCLA.EDU