Article View: comp.arch
Article #21594Re: fast memories (war superscalar)
From: Eugene Brooks
Date: Tue, 06 Jun 1989 00:11
Date: Tue, 06 Jun 1989 00:11
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In article <5128@pt.cs.cmu.edu> jsp@b.gp.cs.cmu.edu (John Pieper) writes: > >Why should we go to custom memory chips? Memory chips which are built to be compatible with a high performance micro destined for commodity use won't be "custom." >With an on-chip cache, there are several ways to implement fast memory without >going to custom chips. The processor needs to support out-of-order memory >operations to support some of the fancier optimizations, but given this, >page-mode DRAMS can be interleaved to give you very good performance, >especially if you have an on-chip cache and load a line at a time. The latest and greatest VLSI micros utilize "page mode" drams and those page mode drams are not fast enough. >Why bend over backwards (inter-company contracts, risk, design cost, etc) >for a 100% when you can have an easy 90% solution? The marginal gain isn't >worth it. Someone who bends over backwards to create a 100 MFLOP micro is not bending over backwards to create a ram chip to go with it. brooks@maddog.llnl.gov, brooks@maddog.uucp
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!ames!hc!lll-winken!vette!brooks From: brooks@vette.llnl.gov (Eugene Brooks) Newsgroups: comp.arch Subject: Re: fast memories (war superscalar) Message-ID: <26450@lll-winken.LLNL.GOV> Date: 6 Jun 89 00:11:37 GMT References: <5128@pt.cs.cmu.edu> Sender: usenet@lll-winken.LLNL.GOV Reply-To: brooks@maddog.llnl.gov (Eugene Brooks) Distribution: usa Organization: Lawrence Livermore National Laboratory Lines: 23