Article View: comp.arch
Article #21623Re: DMA on RISC-based systems
From: Stan Lackey
Date: Wed, 07 Jun 1989 14:30
Date: Wed, 07 Jun 1989 14:30
18 lines
1450 bytes
1450 bytes
In article <620@biar.UUCP> jhood@biar.UUCP (John Hood) writes: >Also note that with modern operating systems that do buffering or disk >caching, there is going to be a bcopy or its moral equivalent in there >somewhere. 1) Is it possible, if not now but possibly in the future, for programmed I/O to _eliminate_ some of the 'bcopy's? 2) This discussion brings to mind one that went around some time ago, which was, is it better to supply a bunch of specialized processors (then bitblt's, now including DMA controllers), or a bunch of identical processors connected together? Theory was, when the bitblt and DMA are done, the other processor(s) can be applied to a compute bound task. It seems to me this might make an interesting product; price/perf range is varied by the number of [identical] processors, and all I/O hardware is very very dumb. -Stan
Technical Details
Message-ID:
<41042@bbn.COM>Path:
arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!csd4.milw.wisc.edu!bbn!bbn.com!slackeyReferences:
<46500067@uxe.cso.uiuc.edu> <181@dg.dg.com> <1989May31.163057.543@utzoo.uucp> <3480@orca.WV.TEK.COM> <185@dg.dg.com> <620@biar.UUCP>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!csd4.milw.wisc.edu!bbn!bbn.com!slackey From: slackey@bbn.com (Stan Lackey) Newsgroups: comp.arch Subject: Re: DMA on RISC-based systems Message-ID: <41042@bbn.COM> Date: 7 Jun 89 14:30:36 GMT References: <46500067@uxe.cso.uiuc.edu> <181@dg.dg.com> <1989May31.163057.543@utzoo.uucp> <3480@orca.WV.TEK.COM> <185@dg.dg.com> <620@biar.UUCP> Sender: news@bbn.COM Reply-To: slackey@BBN.COM (Stan Lackey) Organization: Bolt Beranek and Newman Inc., Cambridge MA Lines: 18