🚀 go-pugleaf

In article <MYX2SzW00XoF42d1lf@andrew.cmu.edu>, hs0l+@andrew.cmu.edu (Hugh Brinkley Sprunt) writes:
> 
> The 386 and 486 architectures claim a virtual address space size of
> 2^46 bytes.  The virtual address is formed from a 14 bit selector
> and a 32 bit offset.  
> 	b) This scheme gives us 2^14 independent address spaces of 2^32 
>      bytes each.  In other words, the virtual memory scheme 
>      consists of as many as 2^14 segments of 2^32 bytes each.
> 
> If (b) is the answer, how does the processor communicate the 14 bits of 
> selector information to the memory mapping hardware/software?

The standard addressing hardware looks the selector up in a local (per 
process) or global selector table.  In this table each selector has a
base physical address, a size, and some privilege bits (r/w/x).  This info
is cached on-chip; when you load a new selector it all gets loaded.

When you get an page fault or other interrupt the faulting selector is 
made available to the interrupt task (it's on the stack or something).

Maybe some Intel guru should fill in the details...

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