🚀 go-pugleaf

In article <24535@shemp.CS.UCLA.EDU> marc@CS.UCLA.EDU (Marc Tremblay) writes:
>Data General claims that the ECL implementation of the Motorola 88000 
>family of processors is 100% compatible with the CMOS version 
>ie. 88100, 88200 (ref. Compcom Spring '89).
>The partitioning of the two implementations is different and lead
>to interesting decisions. For example in the ECL version, the FPU
>is implemented on a separate chip (vs same chip in the CMOS version). 
>Being on a separate chip, the latency of accessing the register
>file located on the integer unit became too long so DG apparently 
>decided to put a "copy" of the 5-port register file on the FPU as well.
>In the CMOS implementation there is a single register file shared
>by the integer unit and the Special Function Unit 1 (FPU).

I can say a little about this.  I am the manager of the group which is
designing the Integer and Floating Point chips.  Unfortunately I can't
say a whole lot more than is already in the COMPCON paper.

The ECL implementation is fully compatible architecturally with the
existing CMOS implementation.  The Binary Compatibility Standard
requires this, at least for user mode.

We didn't just give the FPU its own copy of the register file because
of latency, the bandwidth requirement is also severe.  Moving (up to)
192 bits of operands and results back and forth for each FP op isn't
very attractive.


>This leads to the following question:
>How is consistency maintained between the two register files?
>In the ECL implementation are writes copied between the two register files? 
>If so, it must generate a lot of traffic between the two chips.
>Notice that the consistency has to be maintained in hardware since
>the two implementations are object code compatible.

Consistency is maintained in hardware.  There is a dedicated data bus
connecting the chips which carries the result (if any) of every
instruction.  Needless to say, this bus is pretty fully utilized.  The
scoreboard logic provides the required mechanism for interlocking
instruction issue with the result transfers.  A certain amount of
trickiness is involved to avoid unnecessary stalls.


Chris Moriondo
Principal Hardware Engineer
High-End Systems Development
Data General Corporation

usual disclaimers apply, void where prohibited, your mips may vary...