Article View: comp.arch
Article #21678Re: fast memories (war superscalar)
From: Stan Lackey
Date: Fri, 09 Jun 1989 19:21
Date: Fri, 09 Jun 1989 19:21
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In article <19257@cup.portal.com> bcase@cup.portal.com (Brian bcase Case) writes: >And some of that work is being done now. True, processors will be at >50 MHz and beyond. However, the contention that memories will not keep >up is not necessarily true. I know of an experimental SRAM now being I was just quoting history; for example, in 1977 I designed DRAMS into a project, and the best that could be had were around 100ns. Here we are 12 years later and the fastest are 70 (that suppliers will accept a purchase order for large quantities). In the meantime, processors have gone from 5MHz to 20. That doesn't look like scaling to me. >Memory latency is a problem, but to say that it won't be solved seems >alarmist. I'm not being an alarmist. For example, to deal with faster CPU's than memories (and for other reasons not to the point), caches got invented. I'm just saying that more innovation will be required than just cranking up semiconductor processes. -Stan
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!bbn.com!slackey From: slackey@bbn.com (Stan Lackey) Newsgroups: comp.arch Subject: Re: fast memories (war superscalar) Message-ID: <41190@bbn.COM> Date: 9 Jun 89 19:21:02 GMT References: <5128@pt.cs.cmu.edu> <26450@lll-winken.LLNL.GOV> <40985@bbn.COM> <19257@cup.portal.com> Sender: news@bbn.COM Reply-To: slackey@BBN.COM (Stan Lackey) Distribution: usa Organization: Bolt Beranek and Newman Inc., Cambridge MA Lines: 19