🚀 go-pugleaf

Another RISC bus suggestion:

-> Don't have combined A/D lines.

Although it is very attractive to take your 32 address lines
and your 32 data lines and combine them for a 64 bit wide data path,
it is a lot sillier when you have 256 lines in total (an extra 32
address lines gets lost in the shuffle).

There are a lot of address only data transactions, in a cache coherent system.

Conversely, the block data transfers that we are trying to optimize
with 256 bit transfers would tend to use the data bus for a long time.
(Is this true? I/O transfers use blocks >> 256 bits, but do (should) cache 
systems...)
So address only transactions for processors get blocked by block transfers
for I/O.  Let em pass.