🚀 go-pugleaf

In article <33845@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>
>Could you explain what is meant by "sustain" above?  At least two
>really cool things might be implied by this:
>
>  (1)  In the coming year you'll be building Futurebus+ hardware that
>       can transfer 512 bytes (i.e. 128 words, or 64 bus-widths of data)
>       in 1024 nanoseconds.  This'd be a cache refill from main memory.
>
>  (2)  In the coming year you'll be building Futurebus+ hardware that
>       can do a DMA transfer of 50 Megabytes in 0.1 second.
>
>Are either of the assertions above correct?  {they're based on the assumption
>that (500 MB/sec  /  8 bytes/transfer) = 62.5 Mtransfers/sec = 16ns/transfer
>is the bus cycle time in "sustained" operation}
>

By sustained, I mean that over a period of 0.1 second, the combined traffic
of cache lines (64 bytes on Futurebus+) and large DMA blocks will move more
than 50 Megabytes.  The burst rate, the transfer rate within a single
transaction, will be slightly higher.

>
>Also, folks might think it was a bit smelly to claim high throughput rates
>for a "bus" that only has two or three slots, or for a "bus" that doesn't
>involve a printed circuit backplane board having connectors or sockets for
>separate daughterboards.  Just to lay these types of silly "oh-yeah?"
>questions to rest permanently,
>
>   Does next-years-500MB/sec-Futurebus+ have a mother/daughterboard
>   construction with N>6 connectors and card slots, and will it run
>   at 500 MBytes/sec when fully populated?
>
>Thanks.
>-- 
> -- Mark Johnson	
> 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
>	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}

Yes, I'm talking about a more-or-less standard Futurebus+ backplane
environment with more than 6 populated slots.  Futurebus+ used BTL (Backplane
Transceiver Logic), made by NSC, TI and Signetics.  BTL on a daughtercard
drives a 50 to 60 ohm stripline backplane that is terminated in 39 ohms to
2 volts at both ends.  As long as the edge speed stays longer than 1 nsec.,
this electrical environment is good for data periods of 10 nsec. or less
on a 19 inch rack length backplane with 1 inch board spacing.

The high speed data transfer protocol Futurebus+ uses is called packet mode
and it was invented by Emil Hahn of Signetics.  This protocol uses source
synchronous transmission without transmitting any clock.  Since there is
no clock, there are no bus level set-up or hold times.  The protocol is
also not limited by signal skew, which turns out to be the biggest source
of delay in more standard protocols.  The bottom line is this protocol will
not be a limiting factor in ultimate performance.

The Futurebus+ spec requires a packet implementor to support a minimum
packet speed of 60 MTransfers/sec or 480 MBytes/sec on a 64 bit bus.

As I've tried to show, the electrical environment and the protocol will
both support better than the 16 nsec/transfer rate that Mark asked about.  The
limitation on our performance this next year will be the silicon implementation.

John Theus                                johnt@opus.wv.tek.com
Futurebus+ Parallel Protocol Coordinator
Tektronix, Inc.
Interactive Technologies Div. - shipping the Futurebus-based XD88 workstations