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Article #21922register saving on MIPS csw (was Context switching on RISC chips)
From: Chris Torek
Date: Wed, 03 Jan 1990 05:36
Date: Wed, 03 Jan 1990 05:36
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1344 bytes
In article <34043@mips.mips.COM> mash@mips.COM (John Mashey) writes: >It is good to avoid over-generalizing: > a) Many RISCs do not have as many registers, i.e. in approximate > numbers of 32-bit registers, ignoring system registers: > 88K: 32 > MIPS & HP PA: 64 Also, at least on the MIPS Rx000s, half of those registers are in the FPU (the Rx010), and it is easy to tell whether a process is using the FPU, so (depending on job mix) the number of registers moved by a context switch may be 32 instead of 64. (Note that moving 32 registers implies 32 stores and 32 loads.) Of course, the MIPS reserves 2 of the integer registers to the kernel, so it is actually either 30 registers or 62 registers. . . . (Well, John did say `approximate' :-) ) -- In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163) Domain: chris@cs.umd.edu Path: uunet!mimsy!chris
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!purdue!haven!mimsy!chris From: chris@mimsy.umd.edu (Chris Torek) Newsgroups: comp.arch Subject: register saving on MIPS csw (was Context switching on RISC chips) Message-ID: <21600@mimsy.umd.edu> Date: 3 Jan 90 05:36:39 GMT References: <3167@iitmax.IIT.EDU> <34043@mips.mips.COM> Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742 Lines: 19