Article View: comp.arch
Article #21927Re: register saving on MIPS csw (was Context switching on RISC chips)
From: Roger B.A. Klorese
Date: Wed, 03 Jan 1990 16:48
Date: Wed, 03 Jan 1990 16:48
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In article <21600@mimsy.umd.edu> chris@mimsy.umd.edu (Chris Torek) writes:
>Of course, the MIPS reserves 2 of the integer
>registers to the kernel, so it is actually either 30 registers or 62
>registers. . . .
>
>(Well, John did say `approximate' :-) )
And, of course, R0==0 (hardwired), so that's 29 or 61... I'm pretty sure we
don't save and restore 0 every time... ;-)
--
ROGER B.A. KLORESE MIPS Computer Systems, Inc. phone: +1 408 720-2939
928 E. Arques Ave. Sunnyvale, CA 94086 rogerk@mips.COM
{ames,decwrl,pyramid}!mips!rogerk
"Two guys, one cart, fresh pasta... *you* figure it out." -- Suzanne Sugarbaker
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!tut.cis.ohio-state.edu!zaphod.mps.ohio-state.edu!mips!servitude!rogerk From: rogerk@mips.COM (Roger B.A. Klorese) Newsgroups: comp.arch Subject: Re: register saving on MIPS csw (was Context switching on RISC chips) Message-ID: <34067@mips.mips.COM> Date: 3 Jan 90 16:48:48 GMT References: <3167@iitmax.IIT.EDU> <34043@mips.mips.COM> <21600@mimsy.umd.edu> Sender: news@mips.COM Reply-To: rogerk@mips.COM (Roger B.A. Klorese) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 14