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Article #21933

Re: Covert Channels (orig: Context switching on RISC chips)

#21933
From: William Sommerfeld
Date: Wed, 03 Jan 1990 20:15
25 lines
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As I understood the definition, covert channels can only exist in the
presence of nondiscretionary access controls.  I could be wrong about
that, though.

Multilevel secure operating systems are supposed to be able to prevent
classified data, which a trojan horse has access to, from being leaked
to a process running at a lower security level.

You don't need to be able to get at the register *contents*; instead,
assuming a sufficiently accurate clock, you can notice that a
register-to-register operation which should have taken 100ns actually
took 5us because it trapped and was restarted.

The sender would spin in a loop which either accessed a register or
didn't for each bit..

The reciever would get the time (presumably to microsecond or greater
accuracy), access some of these registers, and get the time again, and
depending on *how long* the access to these registers took, could get
a "1" or a "0" bit.  With a bit more sophistication, you could get
roughly one bit per register per timeslice.
--
Henry Spencer is so much of a  |    Bill Sommerfeld at MIT/Project Athena
minimalist that I often forget |    sommerfeld@mit.edu
he's there - anonymous         |
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From: wesommer@athena.mit.edu (William Sommerfeld)
Newsgroups: comp.arch
Subject: Re: Covert Channels (orig: Context switching on RISC chips)
Message-ID: <WESOMMER.90Jan3151550@anubis.athena.mit.edu>
Date: 3 Jan 90 20:15:50 GMT
References: <3167@iitmax.IIT.EDU> <28573@amdcad.AMD.COM> <52104@srcsip.UUCP>
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In-Reply-To: davidsen@crdos1.crd.ge.COM's message of 3 Jan 90 17:26:52 GMT