🚀 go-pugleaf

In article <579@sagpd1.UUCP>, eprice@sagpd1.UUCP (Eric Price) writes:
>     Seems the other morning whilst I was jump starting my self with
>     a little eXpreSSo, I read a blurb in the buisness section of the
>     San Diego Union about a new floating point type chipster jointly
>     developed by Motorola and United Technologies. Said somthin' 'bout
>     Jillillions of Flops. Still I hav'nt heard 'enny thin' about it.
>     Anyone out there care to squelch the gossip ... or add more fuel
>     to the fire.
> 

I waited a couple of days, hoping someone with more info than I
would post.  No such luck :-), so here goes:

It's a real thing.  On January 3, TRW and Motorola announced a new
chip called the CPUAX.  TRW designed the architecture, which they
call "SuperChip".  Motorola fabs it now, TRW will later.  It has
been fabbed, and is functional.  It was developed under the DoD's
VHSIC program, and will be used by the US Navy in aerospace signal
processing applications.  Later generations are planned, perhaps for
commercial apps.

I know next to nothing about the architecture.  The implementation
is interesting: 0.5 micron CMOS (yes, 0.5), triple layer metal with
salicide, 4 million devices, die size 1.59 X 1.49 inches (NOT cm).
Sorry, I don't know the clock speed.  It's built up of 142 macrocells,
of which 61 must be functional for the part to work.  A small second
chip, the "Universal Processor", operates if a macrocell fails,
dynamically reconfiguring the CPUAX and keeping it functional in
applications requiring high reliability.  200 SP MFLOPS are claimed.

Disclaimers:  I am not a spokesman for Motorola or TRW.  I had nothing
to do with developing the CPUAX.  All of the above is extracted from
press releases.
--
Phil Brownfield, Motorola Semiconductor
{cs.utexas.edu!oakhill, mcdchg}!motaus!phil
oakhill!motaus!phil@cs.utexas.edu probably works