Article View: comp.arch
Article #2211Re: How Caches Work
From: Amos Shapir
Date: Wed, 13 Sep 1989 13:03
Date: Wed, 13 Sep 1989 13:03
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This idea is already in use by some MMU systems - it's called uncacheable (or memory-locked) pages. Such schemes let you specify which pages will be bypassing the cache. (Specifying a page address is equivalent to marking a few address bits, which is what you suggested). -- Amos Shapir amos@taux01.nsc.com or amos@nsc.nsc.com National Semiconductor (Israel) P.O.B. 3007, Herzlia 46104, Israel Tel. +972 52 522261 TWX: 33691, fax: +972-52-558322 34 48 E / 32 10 N (My other cpu is a NS32532)
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!sun-barr!apple!oliveb!amdahl!nsc!taux01!amos From: amos@taux01.UUCP (Amos Shapir) Newsgroups: comp.arch Subject: Re: How Caches Work Message-ID: <2569@taux01.UUCP> Date: 13 Sep 89 13:03:38 GMT References: <21936@cup.portal.com> <1082@cernvax.UUCP> <16306@watdragon.waterloo.edu> <RANG.89Sep10184900@derby.cs.wisc.edu> <8399@boring.cwi.nl> <3989@phri.UUCP> Organization: National Semiconductor (IC) Ltd, Israel Home of the 32532 Lines: 10 Hdate: 13 Elul 5749