🚀 go-pugleaf

In article <5120@crdgw1.crd.ge.com> oconnordm@CRD.GE.COM (Dennis M. O'Connor) writes:
>srg@quick (Spencer Garrett) writes:
>] 	I don't know for sure, but I'd bet there's no nanocode, and
>] 	probably not much microcode.  The only "complex" fpu op is
>] 	sqrt, so maybe they bit the bullet and hardwired it all.
>
>Sqrt is not much more complex than division, actually. Look at
>the manual procedures you were taught for each : very similar.
>I think I've seen array circuit designs that did mul, div and sqrt. 
>I think I remember that once you've built an array divider,
>it's not hard to make it do square-root as well.
>
>Unfortuneately, I can't find the paper I'm thinking of
>in the office. Sorry.

An array divider?  Are you sure?  That's a new one on me.  Who
does division this way?  I know about array multipliers, and folks 
who do division based on Newton Raphson approximation (and sqrts too,
for that matter.)  And there are parts like Weitek's and BIT's that 
generate quotients and roots via iterative methods like radix-4 
non-restoring algorithms.  For those, sqrt is exactly twice as hard, 
because you get only one bit of root per iteration, where division
yields two.

I did see a paper about two years ago in IEEE Trans. on Computers
that showed a way to get two sqrt bits per iteration, but I
recall thinking it would be hard to implement it (then).

Bob Colwell               ..!uunet!mfci!colwell
Multiflow Computer     or colwell@multiflow.com
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