🚀 go-pugleaf

In article <4537@brazos.Rice.edu>, preston@titan.rice.edu (Preston Briggs) writes:
> For (an old, perhaps overworked) example:
> Suppose I want to load a value from
> memory and add it to a register.  On most CISC's I can do it in one
> instruction.  On most RISC's, I have to use 2 instructions.
> On the RISC machine, the value I loaded will still be in a register
> where I can reuse it later.  Of course, we could also use 2 instructions
> on the CISC.  How often does this case arise?  That depends on
> your code and the strength of your optimizer.  The RISC bet (supported
> by dynamic code measurements) is that it happens a lot.

Is this dynamic code measurements of sloppy assembly code or good compiler
generated code or . . .

If the addend is used all that much, some form of code strength reduction
would be warranted.  I suspect the measurements are due to the "cheapness"
of the CISC address arithemetic [using PTR+6, PTR+9, PTR+12, etc., because
it costs nothing in execution time].

Add immediate is used a lot because it is cheap, too.

> So, no matter how fast the CISC people make that "add from memory"
> instruction run, it won't matter much because it isn't used much.

If my memory is still holding up, the probability that you will reuse the
addend is less than 50% with vast numbers of registers (64 or so), and then
only if you spend an immense amount of computational resources doing rather
good data flow analysis.  That says if you have add-from-memory, you're better
off most of the time using it.

The more accurate statement might be that if you design a RISC box, it is
better to design a register-to-register add than a memory-to-register add
or a register-to-memory add because the penalty for the other 50% where it
is not optimal is much less.

> Preston Briggs
> preston@titan.rice.edu

Charles Marslett
chasm@attctc.dallas.tx.us
[I needed some hate mail anyway, ;^)]