Article View: comp.arch
Article #2224Re: How Caches Work
From: Hugh LaMaster
Date: Thu, 14 Sep 1989 04:27
Date: Thu, 14 Sep 1989 04:27
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In article <1184@brazos.Rice.edu> preston@titan.rice.edu (Preston Briggs) writes: >In article <31815@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes: > >>Since there are times when you *do* want array accesses to be cached, >>this might be a case for having two different load instructions, one >>cached and one not cached. That would allow the compiler and/or user >I think you're right. The i860 allows both cached and non-cached loads. You are right. If I had bothered to read the Aug. 89 IEEE Micro before touching my keyboard, I would have known that the i860 has exactly this feature. Good for Intel! Aug. 89 also has a comparison of RISC architectures, although for some reason it ignores MIPSCo... Hugh LaMaster, m/s 233-9, UUCP ames!lamaster NASA Ames Research Center ARPA lamaster@ames.arc.nasa.gov Moffett Field, CA 94035 Phone: (415)694-6117
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!uakari.primate.wisc.edu!ames!ames.arc.nasa.gov!lamaster From: lamaster@ames.arc.nasa.gov (Hugh LaMaster) Newsgroups: comp.arch Subject: Re: How Caches Work Keywords: adaptive caching, Munin Message-ID: <31843@ames.arc.nasa.gov> Date: 14 Sep 89 04:27:05 GMT References: <21936@cup.portal.com> <1082@cernvax.UUCP> <16306@watdragon.waterloo.edu> <RANG.89Sep10184900@derby.cs.wisc.edu> <8399@boring.cwi.nl> <3989@phri.UUCP> <1174@brazos.Rice.edu> <27445@winchester.mips.COM> <31815@ames.arc.nasa.gov> <1184@brazos.Rice.edu> Sender: usenet@ames.arc.nasa.gov Organization: NASA - Ames Research Center Lines: 20