Article View: comp.arch
Article #22265Re: CISC Silent Spring
From: Phil Ronzone
Date: Thu, 08 Feb 1990 18:02
Date: Thu, 08 Feb 1990 18:02
24 lines
1470 bytes
1470 bytes
In article <35647@mips.mips.COM> mash@mips.COM (John Mashey) writes:
>WILL THEY [risc] CATCH UP?
> No:
> Intellectual complexity.
> Longer design cycles.
> Less registers than match current global optimizers.
Hmmm -- maybe we should break RISC into RISC-the-instruction-chip and
RISC-the-el-cheapo-hardware-realization-of-an-instruction-set.
What would we call a chip with say, an R3000 instruction set AND
a microcoded 68XXX instruction set, with a mode bit to flip
between the two?
RISC? CISC? CRISP? :-) RIDICULOUS?
We're going to be able to do it some day.
------Me and my dyslexic keyboard----------------------------------------------
Phil Ronzone Manager Secure UNIX pkr@sgi.COM {decwrl,sun}!sgi!pkr
Silicon Graphics, Inc. "I never vote, it only encourages 'em ..."
-----In honor of Minas, no spell checker was run on this posting---------------
Technical Details
Message-ID:
<3792@odin.SGI.COM>Path:
arc1-ca.pugleaf.net!utzoo!attcan!uunet!tut.cis.ohio-state.edu!zaphod.mps.ohio-state.edu!swrinde!ucsd!ames!sgi!shinobu!odin!maddog!pkrReferences:
<3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <7826@pt.cs.cmu.edu> <3562@odin.SGI.COM> <35647@mips.mips.COM>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!tut.cis.ohio-state.edu!zaphod.mps.ohio-state.edu!swrinde!ucsd!ames!sgi!shinobu!odin!maddog!pkr From: pkr@maddog.sgi.com (Phil Ronzone) Newsgroups: comp.arch Subject: Re: CISC Silent Spring Message-ID: <3792@odin.SGI.COM> Date: 8 Feb 90 18:02:49 GMT References: <3300098@m.cs.uiuc.edu> <771@sce.carleton.ca> <35456@mips.mips.COM> <25cb6b65.702c@polyslo.CalPoly.EDU> <7826@pt.cs.cmu.edu> <3562@odin.SGI.COM> <35647@mips.mips.COM> Sender: news@odin.SGI.COM Organization: Silicon Graphics, Inc., Mountain View, CA Lines: 24