Article View: comp.arch
Article #2227Re: How Caches Work
From: Colin Plumb
Date: Wed, 13 Sep 1989 20:53
Date: Wed, 13 Sep 1989 20:53
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Not cacheing certain accesses is something the i860 does... there are normal loads that the data cache tries to hit on, and pipelined loads that have programmer-visible delay whose values are *not* loaded into the cache. They have some example code for matrix multiplication that loads the rows into cache and uses pipelined loads on the columns to avoid memory delays (it's pipelined with the multiply/accumulates) despite the awful locality of reference. -- -Colin
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!watmath!watdragon!watcsc!colin From: colin@watcsc.waterloo.edu (Colin Plumb) Newsgroups: comp.arch Subject: Re: How Caches Work Keywords: Cache Bypass Message-ID: <1989Sep13.165351.25525@watcsc.waterloo.edu> Date: 13 Sep 89 20:53:48 GMT References: <21936@cup.portal.com> <1082@cernvax.UUCP> <16306@watdragon.waterloo.edu> <RANG.89Sep10184900@derby.cs.wisc.edu> <8399@boring.cwi.nl> <3989@phri.UUCP> <12855@pur-ee.UUCP> Reply-To: colin@watcsc.UUCP (Colin Plumb) Organization: University of Waterloo Computer Science Club Lines: 9