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Article #2232

Re: How Caches Work

#2232
From: Paul Rodman
Date: Thu, 14 Sep 1989 14:48
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In article <31814@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:
>>Along a similar line, the Convex machines cache accesses going to the
>>scalar unit only.  The load/store unit for the vector unit operates
>>directly from main memory to the vector registers.  This is pretty
>
>This is one of the advantages of having
>a vector instruction set, because this is *exactly* what is needed for
>programs of this type.  

What you should have said is: "This is one of the advantages of having
control over whether or not to bypass the cache". A vector instruction
set gives a pretty coarse method of making the choice.

Another point worth noting is that many vector machines only do the
cache bypass if the stride = 1, other strides may go for the cache.
It depends, of course, on how good the memory system is.

pkr
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References: <21936@cup.portal.com> <1082@cernvax.UUCP> <16306@watdragon.waterloo.edu> <RANG.89Sep10184900@derby.cs.wisc.edu> <8399@boring.cwi.nl> <3989@phri.UUCP> <MCCALPIN.89Sep12111256@masig3.ocean.fsu.edu> <31814@ames.arc.nasa.gov>

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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!cs.utexas.edu!uunet!yale!mfci!rodman
From: rodman@mfci.UUCP (Paul Rodman)
Newsgroups: comp.arch
Subject: Re: How Caches Work
Message-ID: <1029@m3.mfci.UUCP>
Date: 14 Sep 89 14:48:54 GMT
References: <21936@cup.portal.com> <1082@cernvax.UUCP> <16306@watdragon.waterloo.edu> <RANG.89Sep10184900@derby.cs.wisc.edu> <8399@boring.cwi.nl> <3989@phri.UUCP> <MCCALPIN.89Sep12111256@masig3.ocean.fsu.edu> <31814@ames.arc.nasa.gov>
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