🚀 go-pugleaf

In article <11112@encore.Encore.COM> jkenton@pinocchio.UUCP (Jeff Kenton) writes:
>In article <9708@spool.cs.wisc.edu> shekita@provolone.cs.wisc.edu (E Shekita) writes:
>>Could any of you hardware designers in the trenches out there 
>>tell me whether 64-bit addresses will become reality anytime soon.
>>If so, how soon. If not, why... And how about in the distant future, say,
>>10 years, which is virtually an eternity in hardware design.
>>
>
>Here's a guess from the land of software, related to a discussion I had
>yesterday with a friend (thanks Carl):
>
>	o  When the change comes, it will be to 64 bits -- not 40, 48 or 60.
>
I would personally prefer a 64 bit word size with either straight
48 bit addresses or else 64 bit addresses with the top 16 bits used
as a segment number.  Why?  Because it is very hard to fit
64 bits of address into a 64 bit instruction and still have room
for e.g. the opcode.  I'm a real proponent of fixed size instructions,
and I don't think two instructions should be required just to load
an address.

Actually, I'll go further and say I'm not sure that a 64 bit machine
really needs to fully support 64 bit integers.  There should definitely
be 64 bit add/subtract, boolean, shifts, and anything else which scales
linearly with word size, but I think the largest integer multiply
supported need only be 48x48 -> 96, with the corresponding divide
96/48 -> 48,48.  A 48 bit multiplier is huge, let alone a 64 bit,
and this would let the floating point multiplier handle integer
multiplies (assuming a 16 bit exponent 48 bit fraction floating
point representation).

Does anyone have an application which frequently multiplies 49-64
bit integers?  I'm not talking about indefinite precision arithmetic,
but about numbers of exactly that many bits.  Please let me know.

Of course, I'm not an electrical engineer, and I'm sure that device
densities will probably get to the point where nobody worries about
space for an extra 64x64 multiplier.