Article View: comp.arch
Article #22343Re: New instructions for RISCs (was Re: Byte ordering)
From: Peter da Silva
Date: Sun, 11 Feb 1990 19:47
Date: Sun, 11 Feb 1990 19:47
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In article <139@oscsunb.osc.edu> djh@osc.edu (David Heisterberg) writes:
> I don't understand your comment about needing a "load word bit-aligned"
> operator; CRAYs certainly don't have such a thing, and are not byte adressable,
> yet the scalar merge is a useful instruction.
The most common compute-intensive use of scalar merge (your terminology) in
workstations seems to be in display management: the BitBlt operator in one of
it's many guises. And BitBlt would benefit from bit-aligned LOAD, an operation
that's no more expensive in real-estate than byte-aligned LOAD... a barrel-
shifter is a barrel-shifter is a rose.
--
_--_|\ Peter da Silva. +1 713 274 5180. <peter@ficc.uu.net>.
/ \
\_.--._/ Xenix Support -- it's not just a job, it's an adventure!
v "Have you hugged your wolf today?" `-_-'
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arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!rpi!zaphod.mps.ohio-state.edu!lavaca.uh.edu!uhnix1!sugar!ficc!peterReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!rpi!zaphod.mps.ohio-state.edu!lavaca.uh.edu!uhnix1!sugar!ficc!peter From: peter@ficc.uu.net (Peter da Silva) Newsgroups: comp.arch Subject: Re: New instructions for RISCs (was Re: Byte ordering) Keywords: bitblt Message-ID: <Q0P1T38xds13@ficc.uu.net> Date: 11 Feb 90 19:47:41 GMT References: <7345@pdn.paradyne.com> <168@zds-ux.UUCP> <79N15F5xds13@ficc.uu.net> <139@oscsunb.osc.edu> Reply-To: peter@ficc.uu.net (Peter da Silva) Organization: Xenix Support, FICC Lines: 10