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Article #22368

clock-rate lockstep

#22368
From: Henry Spencer
Date: Mon, 12 Feb 1990 22:53
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In article <7372@pdn.paradyne.com> alan@oz.paradyne.com (Alan Lovejoy) writes:
>... Oh, SPARC is scaleable?
>That's nice.  It hasn't seemed to provide it with any particular clock rate
>advantage so far (both the SPARC and the 88k are in production at 33MHz,
>for instance...

As John Mashey has pointed out, main-line MOS production clock speeds are
limited as much by test equipment as by anything else, because you can't
ship chips unless you know they work.  Since everybody is buying from
the same test-equipment manufacturers, XYZ Vaporchips *can't* get much
of a clock-speed lead on ABC Silicrud unless ABC has run into trouble
of some kind.  Claims of scaleability are relevant to future plans and
multi-chip high-end implementations, but don't affect competition in the
one-chip arena very much.
-- 
SVR4:  every feature you ever |     Henry Spencer at U of Toronto Zoology
wanted, and plenty you didn't.| uunet!attcan!utzoo!henry henry@zoo.toronto.edu
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Message-ID: <1990Feb12.225322.20664@utzoo.uucp>
Path: arc1-ca.pugleaf.net!utzoo!henry
References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP> <2100@crdos1.crd.ge.COM> <7356@pdn.paradyne.com> <2113@crdos1.crd.ge.COM> <7372@pdn.paradyne.com>

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Newsgroups: comp.arch
Path: arc1-ca.pugleaf.net!utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: clock-rate lockstep
Message-ID: <1990Feb12.225322.20664@utzoo.uucp>
Organization: U of Toronto Zoology
References: <8905@portia.Stanford.EDU> <160@zds-ux.UUCP> <2100@crdos1.crd.ge.COM> <7356@pdn.paradyne.com> <2113@crdos1.crd.ge.COM> <7372@pdn.paradyne.com>
Date: Mon, 12 Feb 90 22:53:22 GMT