Re: New instructions for RISCs (was Re: Byte ordering)

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Article #22436

#22436

From: Dan Hendrickson
Date: Tue, 13 Feb 1990 14:40

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}BTW, does anyone have an instruction format which uses the
}source register specifiers as an immediate small constant
}instead of a register specifier?
}-- 
Every ALU instruction in SPARC can use one of the source register fields
as a small (11 bit?) signed immediate field.  In the MIPS architecture,
there are seperate instructions for instructions which use immediate
values (16 bit signed).

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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!mailrus!cs.utexas.edu!halley!danh

References: <7345@pdn.paradyne.com} <168@zds-ux.UUCP} <7366@pdn.paradyne.com} <1990Feb10.154033.4271@mentor.com}

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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!mailrus!cs.utexas.edu!halley!danh
From: danh@halley.UUCP (Dan Hendrickson)
Newsgroups: comp.arch
Subject: Re: New instructions for RISCs (was Re: Byte ordering)
Message-ID: <668@halley.UUCP>
Date: 13 Feb 90 14:40:40 GMT
References: <7345@pdn.paradyne.com} <168@zds-ux.UUCP} <7366@pdn.paradyne.com} <1990Feb10.154033.4271@mentor.com}
Reply-To: danh@halley.UUCP (Dan Hendrickson)
Organization: Tandem Computers, Austin, TX
Lines: 8

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