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>In article <1229@m3.mfci.UUCP> colwell@mfci.UUCP (Robert Colwell) writes:
>>In article <38462@apple.Apple.COM> baum@apple.UUCP ( me! ) writes:
>> ....flames about smooth pipelining & CISC....

>But this is only true if you are setting out to design a CISC starting
>from a clean slate.  It's not clear to me why anyone would do that, 
>unless they had goals other than performance uppermost in their minds

Well, I think my point was that you would start with a clean slate; after
all, that's what RISC did. My furhter point was that some of the CISCy
features that people think of as awful (e.g. reg.-mem instructions) 
a). can be implemented without adversely
b). use of these features can improve performance (cut # of cycles) of programs

Another way to look at a reg-mem architecture is as a limited
superscalar architecture. If you look from a pipelining point of view,
you'll notice that the address calculation and execution (of different
instructions) occur in parallel; parallelism that does not occur in
load/store architectures. Note that you still have to use instruction 
scheduling in order to avoid interlocks, but IBM talked about doing that
to improve performance at the first ASPLOS conference.

Current RISC design is based on some level of compiler technology. I believe
that current compiler technology can go further. In fact, one of the series
of patents that IBM got on the 801 was a method for choosing which address
mode to use, i.e. when to load into a register and re-use the value, and
when to use a reg-memory instruction because it won't get re-used.

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		  baum@apple.com		(408)974-3385
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