Article View: comp.arch
Article #22458Re: Time between memory failure
From: H.Shrikumar{shri
Date: Sat, 10 Feb 1990 22:29
Date: Sat, 10 Feb 1990 22:29
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1596 bytes
In article <1911@sunquest.UUCP> terry@sunquest.UUCP (Terry) responds to: ><3938@ganymede.inmos.co.uk>, davidb@braa.inmos.co.uk (David Boreham) >> No personal computer or workstation built nowadays needs parity or EDC. > >Now wait. I've seen a couple of instances of memory parity errors on >fairly new PCs. Are you really trying to say that I'd be better off Just to comment that in the memory design,the tightest timing path is the parity checker/generator. And with so much pressure to tighten the memory timing, this path "might" be underdesigned. One of the PC's back home gives a RAM ERROR if the room gets a bit hotter that usual... I think the DRAMs are fine, `cos the same DRAMs work well with other PC's; but rather the parity checker timing is marginal and acts up if the mercury creeps up a few degrees. If only I could disable the parity check when I am playing games on a warm day :-) -- shrikumar ( shri@ccs1.cs.umass.edu, shri@ncst.in )
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From: shri@ccs1.cs.umass.edu (H.Shrikumar{shri@ncst.in})
Newsgroups: comp.arch
Subject: Re: Time between memory failure
Keywords: parity, memory, failure
Message-ID: <9975@dime.cs.umass.edu>
Date: 10 Feb 90 22:29:00 GMT
References: <1911@sunquest.UUCP>
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Reply-To: shri@ccs1.cs.umass.edu (H.Shrikumar{shri@ncst.in})
Organization: University of Massachusetts, Amherst
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