🚀 go-pugleaf

>From: sritacco@hpdmd48.HP.COM (Steve Ritacco)
>
>Why is it that the RIOS has a bigger data cache than instruction cache?
>This defies conventional wisdom.  Data caches are less effective than
>instruction caches and are usually made small because their hit ratio
>doesn't increase with size as rapidly as instruction cache.  If I had to
>guess what is going on, I would guess that access to the I-cache is
>very wide, to suport super-scaler, so they crammed all they could on
>the CPU chip.  This seems to be pretty effective.  IBM has shown the
>super-scaler architecture works, which up to this point I wasn't convinced
>of.  The benifits are tangible.  A 20MgHz CPU with 8K I-cache and 32K
>D-cache SPECmarked at 22.something.  That is quite impressive.  The R3000
>which to date seemed the most efficient CPU/system implementation has
>been displaced for the moment.

Huh?!?

I-caches get better hit rates than D-caches, but you quickly reach a
point of diminishing returns - your I-cache hit rate is so good than
improving it doesn't make too much difference to your performance.
Moreover, if your memory system cycles comparable to your processor,
but just has a large latency, then you can suck instructions out of
memory, except for branches.

Just went to a talk by Mudge of Michigan, who are building a GaAs MIPS
6000, where the speaker had to justify I-cache bigger than D-cache.
In this case, they wanted a direct mapped virtual primary D-cache,
so the D-cache size was limited by the page size of the architecture,
to avoid synonym problems.  Since you don't worry about synonyms in the
I-cache, the I-cache could be made larger.

--
Andy Glew, aglew@uiuc.edu